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完善龙芯指令元信息表格
This commit is contained in:
chai2010
@@ -568,7 +568,11 @@ func parsePage(num int, p pdf.Page, isFP bool) (ops []string, opstrs map[string]
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if strings.HasPrefix(op, "AM") {
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instArgs = "arg_rd, arg_rk, arg_rj"
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}
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instFormat := fmt.Sprintf("{mask: %s, value: %s, args: instArgs{%s}},", binstrToHex(binMask), binstrToHex(binValue), instArgs)
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instFormat := fmt.Sprintf(
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"{mask: %s, value: %s, op: A%s, args: instArgs{%s}},",
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binstrToHex(binMask), binstrToHex(binValue),
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op, instArgs,
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)
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instFormats[op] = instFormat
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i = j // next instruction
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@@ -816,130 +816,130 @@ var _Anames = [...]string{
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// 指令编码信息表
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var _AOpContextTable = [...]_OpContextType{
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AADDI_D: {mask: 0xffc00000, value: 0x02c00000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
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AADDI_W: {mask: 0xffc00000, value: 0x02800000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
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AADDU16I_D: {mask: 0xfc000000, value: 0x10000000, args: instArgs{arg_rd, arg_rj, arg_si16_25_10}},
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AADD_D: {mask: 0xffff8000, value: 0x00108000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AADD_W: {mask: 0xffff8000, value: 0x00100000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AALSL_D: {mask: 0xfffe0000, value: 0x002c0000, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AALSL_W: {mask: 0xfffe0000, value: 0x00040000, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AALSL_WU: {mask: 0xfffe0000, value: 0x00060000, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AAMADD_B: {mask: 0xffff8000, value: 0x385d0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_D: {mask: 0xffff8000, value: 0x38618000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_B: {mask: 0xffff8000, value: 0x385f0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_D: {mask: 0xffff8000, value: 0x386a8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_H: {mask: 0xffff8000, value: 0x385f8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_W: {mask: 0xffff8000, value: 0x386a0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_H: {mask: 0xffff8000, value: 0x385d8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_W: {mask: 0xffff8000, value: 0x38610000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_D: {mask: 0xffff8000, value: 0x38628000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_DB_D: {mask: 0xffff8000, value: 0x386b8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_DB_W: {mask: 0xffff8000, value: 0x386b0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_W: {mask: 0xffff8000, value: 0x38620000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_B: {mask: 0xffff8000, value: 0x38580000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_D: {mask: 0xffff8000, value: 0x38598000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_B: {mask: 0xffff8000, value: 0x385a0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_D: {mask: 0xffff8000, value: 0x385b8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_H: {mask: 0xffff8000, value: 0x385a8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_W: {mask: 0xffff8000, value: 0x385b0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_H: {mask: 0xffff8000, value: 0x38588000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_W: {mask: 0xffff8000, value: 0x38590000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_D: {mask: 0xffff8000, value: 0x38658000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_DB_D: {mask: 0xffff8000, value: 0x386e8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_DB_DU: {mask: 0xffff8000, value: 0x38708000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_DB_W: {mask: 0xffff8000, value: 0x386e0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_DB_WU: {mask: 0xffff8000, value: 0x38700000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_DU: {mask: 0xffff8000, value: 0x38678000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_W: {mask: 0xffff8000, value: 0x38650000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_WU: {mask: 0xffff8000, value: 0x38670000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_D: {mask: 0xffff8000, value: 0x38668000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_DB_D: {mask: 0xffff8000, value: 0x386f8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_DB_DU: {mask: 0xffff8000, value: 0x38718000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_DB_W: {mask: 0xffff8000, value: 0x386f0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_DB_WU: {mask: 0xffff8000, value: 0x38710000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_DU: {mask: 0xffff8000, value: 0x38688000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_W: {mask: 0xffff8000, value: 0x38660000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMIN_WU: {mask: 0xffff8000, value: 0x38680000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMOR_D: {mask: 0xffff8000, value: 0x38638000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMOR_DB_D: {mask: 0xffff8000, value: 0x386c8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMOR_DB_W: {mask: 0xffff8000, value: 0x386c0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMOR_W: {mask: 0xffff8000, value: 0x38630000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_B: {mask: 0xffff8000, value: 0x385c0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_D: {mask: 0xffff8000, value: 0x38608000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_DB_B: {mask: 0xffff8000, value: 0x385e0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_DB_D: {mask: 0xffff8000, value: 0x38698000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_DB_H: {mask: 0xffff8000, value: 0x385e8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_DB_W: {mask: 0xffff8000, value: 0x38690000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_H: {mask: 0xffff8000, value: 0x385c8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMSWAP_W: {mask: 0xffff8000, value: 0x38600000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMXOR_D: {mask: 0xffff8000, value: 0x38648000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMXOR_DB_D: {mask: 0xffff8000, value: 0x386d8000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMXOR_DB_W: {mask: 0xffff8000, value: 0x386d0000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMXOR_W: {mask: 0xffff8000, value: 0x38640000, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAND: {mask: 0xffff8000, value: 0x00148000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AANDI: {mask: 0xffc00000, value: 0x03400000, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
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AANDN: {mask: 0xffff8000, value: 0x00168000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AASRTGT_D: {mask: 0xffff801f, value: 0x00018000, args: instArgs{arg_rj, arg_rk}},
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AASRTLE_D: {mask: 0xffff801f, value: 0x00010000, args: instArgs{arg_rj, arg_rk}},
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AB: {mask: 0xfc000000, value: 0x50000000, args: instArgs{arg_offset_25_0}},
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ABCEQZ: {mask: 0xfc000300, value: 0x48000000, args: instArgs{arg_cj, arg_offset_20_0}},
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ABCNEZ: {mask: 0xfc000300, value: 0x48000100, args: instArgs{arg_cj, arg_offset_20_0}},
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ABEQ: {mask: 0xfc000000, value: 0x58000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABEQZ: {mask: 0xfc000000, value: 0x40000000, args: instArgs{arg_rj, arg_offset_20_0}},
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ABGE: {mask: 0xfc000000, value: 0x64000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABGEU: {mask: 0xfc000000, value: 0x6c000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABITREV_4B: {mask: 0xfffffc00, value: 0x00004800, args: instArgs{arg_rd, arg_rj}},
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ABITREV_8B: {mask: 0xfffffc00, value: 0x00004c00, args: instArgs{arg_rd, arg_rj}},
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ABITREV_D: {mask: 0xfffffc00, value: 0x00005400, args: instArgs{arg_rd, arg_rj}},
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ABITREV_W: {mask: 0xfffffc00, value: 0x00005000, args: instArgs{arg_rd, arg_rj}},
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ABL: {mask: 0xfc000000, value: 0x54000000, args: instArgs{arg_offset_25_0}},
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ABLT: {mask: 0xfc000000, value: 0x60000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABLTU: {mask: 0xfc000000, value: 0x68000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABNE: {mask: 0xfc000000, value: 0x5c000000, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
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ABNEZ: {mask: 0xfc000000, value: 0x44000000, args: instArgs{arg_rj, arg_offset_20_0}},
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ABREAK: {mask: 0xffff8000, value: 0x002a0000, args: instArgs{arg_code_14_0}},
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ABSTRINS_D: {mask: 0xffc00000, value: 0x00800000, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
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ABSTRINS_W: {mask: 0xffe08000, value: 0x00600000, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
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ABSTRPICK_D: {mask: 0xffc00000, value: 0x00c00000, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
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ABSTRPICK_W: {mask: 0xffe08000, value: 0x00608000, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
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ABYTEPICK_D: {mask: 0xfffc0000, value: 0x000c0000, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa3_17_15}},
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ABYTEPICK_W: {mask: 0xfffe0000, value: 0x00080000, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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ACACOP: {mask: 0xffc00000, value: 0x06000000, args: instArgs{arg_code_4_0, arg_rj, arg_si12_21_10}},
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ACLO_D: {mask: 0xfffffc00, value: 0x00002000, args: instArgs{arg_rd, arg_rj}},
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ACLO_W: {mask: 0xfffffc00, value: 0x00001000, args: instArgs{arg_rd, arg_rj}},
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ACLZ_D: {mask: 0xfffffc00, value: 0x00002400, args: instArgs{arg_rd, arg_rj}},
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ACLZ_W: {mask: 0xfffffc00, value: 0x00001400, args: instArgs{arg_rd, arg_rj}},
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ACPUCFG: {mask: 0xfffffc00, value: 0x00006c00, args: instArgs{arg_rd, arg_rj}},
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ACRCC_W_B_W: {mask: 0xffff8000, value: 0x00260000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRCC_W_D_W: {mask: 0xffff8000, value: 0x00278000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRCC_W_H_W: {mask: 0xffff8000, value: 0x00268000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRCC_W_W_W: {mask: 0xffff8000, value: 0x00270000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRC_W_B_W: {mask: 0xffff8000, value: 0x00240000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRC_W_D_W: {mask: 0xffff8000, value: 0x00258000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRC_W_H_W: {mask: 0xffff8000, value: 0x00248000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACRC_W_W_W: {mask: 0xffff8000, value: 0x00250000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ACSRRD: {mask: 0xff0003e0, value: 0x04000000, args: instArgs{arg_rd, arg_csr_23_10}},
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ACSRWR: {mask: 0xff0003e0, value: 0x04000020, args: instArgs{arg_rd, arg_csr_23_10}},
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ACSRXCHG: {mask: 0xff000000, value: 0x04000000, args: instArgs{arg_rd, arg_rj, arg_csr_23_10}},
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ACTO_D: {mask: 0xfffffc00, value: 0x00002800, args: instArgs{arg_rd, arg_rj}},
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ACTO_W: {mask: 0xfffffc00, value: 0x00001800, args: instArgs{arg_rd, arg_rj}},
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ACTZ_D: {mask: 0xfffffc00, value: 0x00002c00, args: instArgs{arg_rd, arg_rj}},
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ACTZ_W: {mask: 0xfffffc00, value: 0x00001c00, args: instArgs{arg_rd, arg_rj}},
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ADBAR: {mask: 0xffff8000, value: 0x38720000, args: instArgs{arg_hint_14_0}},
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ADBCL: {mask: 0xffff8000, value: 0x002a8000, args: instArgs{arg_code_14_0}},
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ADIV_D: {mask: 0xffff8000, value: 0x00220000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ADIV_DU: {mask: 0xffff8000, value: 0x00230000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ADIV_W: {mask: 0xffff8000, value: 0x00200000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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ADIV_WU: {mask: 0xffff8000, value: 0x00210000, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AERTN: {mask: 0xffffffff, value: 0x06483800, args: instArgs{}},
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AEXT_W_B: {mask: 0xfffffc00, value: 0x00005c00, args: instArgs{arg_rd, arg_rj}},
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AEXT_W_H: {mask: 0xfffffc00, value: 0x00005800, args: instArgs{arg_rd, arg_rj}},
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AFABS_D: {mask: 0xfffffc00, value: 0x01140800, args: instArgs{arg_fd, arg_fj}},
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AFABS_S: {mask: 0xfffffc00, value: 0x01140400, args: instArgs{arg_fd, arg_fj}},
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AFADD_D: {mask: 0xffff8000, value: 0x01010000, args: instArgs{arg_fd, arg_fj, arg_fk}},
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AFADD_S: {mask: 0xffff8000, value: 0x01008000, args: instArgs{arg_fd, arg_fj, arg_fk}},
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AFCLASS_D: {mask: 0xfffffc00, value: 0x01143800, args: instArgs{arg_fd, arg_fj}},
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AFCLASS_S: {mask: 0xfffffc00, value: 0x01143400, args: instArgs{arg_fd, arg_fj}},
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AADDI_D: {mask: 0xffc00000, value: 0x02c00000, op: AADDI_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
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AADDI_W: {mask: 0xffc00000, value: 0x02800000, op: AADDI_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
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AADDU16I_D: {mask: 0xfc000000, value: 0x10000000, op: AADDU16I_D, args: instArgs{arg_rd, arg_rj, arg_si16_25_10}},
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AADD_D: {mask: 0xffff8000, value: 0x00108000, op: AADD_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AADD_W: {mask: 0xffff8000, value: 0x00100000, op: AADD_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
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AALSL_D: {mask: 0xfffe0000, value: 0x002c0000, op: AALSL_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AALSL_W: {mask: 0xfffe0000, value: 0x00040000, op: AALSL_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AALSL_WU: {mask: 0xfffe0000, value: 0x00060000, op: AALSL_WU, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
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AAMADD_B: {mask: 0xffff8000, value: 0x385d0000, op: AAMADD_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_D: {mask: 0xffff8000, value: 0x38618000, op: AAMADD_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_B: {mask: 0xffff8000, value: 0x385f0000, op: AAMADD_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_D: {mask: 0xffff8000, value: 0x386a8000, op: AAMADD_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_H: {mask: 0xffff8000, value: 0x385f8000, op: AAMADD_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_DB_W: {mask: 0xffff8000, value: 0x386a0000, op: AAMADD_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_H: {mask: 0xffff8000, value: 0x385d8000, op: AAMADD_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMADD_W: {mask: 0xffff8000, value: 0x38610000, op: AAMADD_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_D: {mask: 0xffff8000, value: 0x38628000, op: AAMAND_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_DB_D: {mask: 0xffff8000, value: 0x386b8000, op: AAMAND_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_DB_W: {mask: 0xffff8000, value: 0x386b0000, op: AAMAND_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMAND_W: {mask: 0xffff8000, value: 0x38620000, op: AAMAND_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_B: {mask: 0xffff8000, value: 0x38580000, op: AAMCAS_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_D: {mask: 0xffff8000, value: 0x38598000, op: AAMCAS_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_B: {mask: 0xffff8000, value: 0x385a0000, op: AAMCAS_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_D: {mask: 0xffff8000, value: 0x385b8000, op: AAMCAS_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_H: {mask: 0xffff8000, value: 0x385a8000, op: AAMCAS_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_DB_W: {mask: 0xffff8000, value: 0x385b0000, op: AAMCAS_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_H: {mask: 0xffff8000, value: 0x38588000, op: AAMCAS_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMCAS_W: {mask: 0xffff8000, value: 0x38590000, op: AAMCAS_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
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AAMMAX_D: {mask: 0xffff8000, value: 0x38658000, op: AAMMAX_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_DB_D: {mask: 0xffff8000, value: 0x386e8000, op: AAMMAX_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_DB_DU: {mask: 0xffff8000, value: 0x38708000, op: AAMMAX_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_DB_W: {mask: 0xffff8000, value: 0x386e0000, op: AAMMAX_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_DB_WU: {mask: 0xffff8000, value: 0x38700000, op: AAMMAX_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_DU: {mask: 0xffff8000, value: 0x38678000, op: AAMMAX_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_W: {mask: 0xffff8000, value: 0x38650000, op: AAMMAX_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMAX_WU: {mask: 0xffff8000, value: 0x38670000, op: AAMMAX_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_D: {mask: 0xffff8000, value: 0x38668000, op: AAMMIN_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_DB_D: {mask: 0xffff8000, value: 0x386f8000, op: AAMMIN_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_DB_DU: {mask: 0xffff8000, value: 0x38718000, op: AAMMIN_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_DB_W: {mask: 0xffff8000, value: 0x386f0000, op: AAMMIN_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_DB_WU: {mask: 0xffff8000, value: 0x38710000, op: AAMMIN_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_DU: {mask: 0xffff8000, value: 0x38688000, op: AAMMIN_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_W: {mask: 0xffff8000, value: 0x38660000, op: AAMMIN_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMMIN_WU: {mask: 0xffff8000, value: 0x38680000, op: AAMMIN_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMOR_D: {mask: 0xffff8000, value: 0x38638000, op: AAMOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMOR_DB_D: {mask: 0xffff8000, value: 0x386c8000, op: AAMOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMOR_DB_W: {mask: 0xffff8000, value: 0x386c0000, op: AAMOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMOR_W: {mask: 0xffff8000, value: 0x38630000, op: AAMOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_B: {mask: 0xffff8000, value: 0x385c0000, op: AAMSWAP_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_D: {mask: 0xffff8000, value: 0x38608000, op: AAMSWAP_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_DB_B: {mask: 0xffff8000, value: 0x385e0000, op: AAMSWAP_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_DB_D: {mask: 0xffff8000, value: 0x38698000, op: AAMSWAP_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_DB_H: {mask: 0xffff8000, value: 0x385e8000, op: AAMSWAP_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_DB_W: {mask: 0xffff8000, value: 0x38690000, op: AAMSWAP_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_H: {mask: 0xffff8000, value: 0x385c8000, op: AAMSWAP_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMSWAP_W: {mask: 0xffff8000, value: 0x38600000, op: AAMSWAP_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMXOR_D: {mask: 0xffff8000, value: 0x38648000, op: AAMXOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMXOR_DB_D: {mask: 0xffff8000, value: 0x386d8000, op: AAMXOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMXOR_DB_W: {mask: 0xffff8000, value: 0x386d0000, op: AAMXOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAMXOR_W: {mask: 0xffff8000, value: 0x38640000, op: AAMXOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
AAND: {mask: 0xffff8000, value: 0x00148000, op: AAND, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AANDI: {mask: 0xffc00000, value: 0x03400000, op: AANDI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
|
||||
AANDN: {mask: 0xffff8000, value: 0x00168000, op: AANDN, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AASRTGT_D: {mask: 0xffff801f, value: 0x00018000, op: AASRTGT_D, args: instArgs{arg_rj, arg_rk}},
|
||||
AASRTLE_D: {mask: 0xffff801f, value: 0x00010000, op: AASRTLE_D, args: instArgs{arg_rj, arg_rk}},
|
||||
AB: {mask: 0xfc000000, value: 0x50000000, op: AB, args: instArgs{arg_offset_25_0}},
|
||||
ABCEQZ: {mask: 0xfc000300, value: 0x48000000, op: ABCEQZ, args: instArgs{arg_cj, arg_offset_20_0}},
|
||||
ABCNEZ: {mask: 0xfc000300, value: 0x48000100, op: ABCNEZ, args: instArgs{arg_cj, arg_offset_20_0}},
|
||||
ABEQ: {mask: 0xfc000000, value: 0x58000000, op: ABEQ, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABEQZ: {mask: 0xfc000000, value: 0x40000000, op: ABEQZ, args: instArgs{arg_rj, arg_offset_20_0}},
|
||||
ABGE: {mask: 0xfc000000, value: 0x64000000, op: ABGE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABGEU: {mask: 0xfc000000, value: 0x6c000000, op: ABGEU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABITREV_4B: {mask: 0xfffffc00, value: 0x00004800, op: ABITREV_4B, args: instArgs{arg_rd, arg_rj}},
|
||||
ABITREV_8B: {mask: 0xfffffc00, value: 0x00004c00, op: ABITREV_8B, args: instArgs{arg_rd, arg_rj}},
|
||||
ABITREV_D: {mask: 0xfffffc00, value: 0x00005400, op: ABITREV_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ABITREV_W: {mask: 0xfffffc00, value: 0x00005000, op: ABITREV_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ABL: {mask: 0xfc000000, value: 0x54000000, op: ABL, args: instArgs{arg_offset_25_0}},
|
||||
ABLT: {mask: 0xfc000000, value: 0x60000000, op: ABLT, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABLTU: {mask: 0xfc000000, value: 0x68000000, op: ABLTU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABNE: {mask: 0xfc000000, value: 0x5c000000, op: ABNE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
|
||||
ABNEZ: {mask: 0xfc000000, value: 0x44000000, op: ABNEZ, args: instArgs{arg_rj, arg_offset_20_0}},
|
||||
ABREAK: {mask: 0xffff8000, value: 0x002a0000, op: ABREAK, args: instArgs{arg_code_14_0}},
|
||||
ABSTRINS_D: {mask: 0xffc00000, value: 0x00800000, op: ABSTRINS_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
|
||||
ABSTRINS_W: {mask: 0xffe08000, value: 0x00600000, op: ABSTRINS_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
|
||||
ABSTRPICK_D: {mask: 0xffc00000, value: 0x00c00000, op: ABSTRPICK_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
|
||||
ABSTRPICK_W: {mask: 0xffe08000, value: 0x00608000, op: ABSTRPICK_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
|
||||
ABYTEPICK_D: {mask: 0xfffc0000, value: 0x000c0000, op: ABYTEPICK_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa3_17_15}},
|
||||
ABYTEPICK_W: {mask: 0xfffe0000, value: 0x00080000, op: ABYTEPICK_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
|
||||
ACACOP: {mask: 0xffc00000, value: 0x06000000, op: ACACOP, args: instArgs{arg_code_4_0, arg_rj, arg_si12_21_10}},
|
||||
ACLO_D: {mask: 0xfffffc00, value: 0x00002000, op: ACLO_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ACLO_W: {mask: 0xfffffc00, value: 0x00001000, op: ACLO_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ACLZ_D: {mask: 0xfffffc00, value: 0x00002400, op: ACLZ_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ACLZ_W: {mask: 0xfffffc00, value: 0x00001400, op: ACLZ_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ACPUCFG: {mask: 0xfffffc00, value: 0x00006c00, op: ACPUCFG, args: instArgs{arg_rd, arg_rj}},
|
||||
ACRCC_W_B_W: {mask: 0xffff8000, value: 0x00260000, op: ACRCC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRCC_W_D_W: {mask: 0xffff8000, value: 0x00278000, op: ACRCC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRCC_W_H_W: {mask: 0xffff8000, value: 0x00268000, op: ACRCC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRCC_W_W_W: {mask: 0xffff8000, value: 0x00270000, op: ACRCC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRC_W_B_W: {mask: 0xffff8000, value: 0x00240000, op: ACRC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRC_W_D_W: {mask: 0xffff8000, value: 0x00258000, op: ACRC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRC_W_H_W: {mask: 0xffff8000, value: 0x00248000, op: ACRC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACRC_W_W_W: {mask: 0xffff8000, value: 0x00250000, op: ACRC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ACSRRD: {mask: 0xff0003e0, value: 0x04000000, op: ACSRRD, args: instArgs{arg_rd, arg_csr_23_10}},
|
||||
ACSRWR: {mask: 0xff0003e0, value: 0x04000020, op: ACSRWR, args: instArgs{arg_rd, arg_csr_23_10}},
|
||||
ACSRXCHG: {mask: 0xff000000, value: 0x04000000, op: ACSRXCHG, args: instArgs{arg_rd, arg_rj, arg_csr_23_10}},
|
||||
ACTO_D: {mask: 0xfffffc00, value: 0x00002800, op: ACTO_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ACTO_W: {mask: 0xfffffc00, value: 0x00001800, op: ACTO_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ACTZ_D: {mask: 0xfffffc00, value: 0x00002c00, op: ACTZ_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ACTZ_W: {mask: 0xfffffc00, value: 0x00001c00, op: ACTZ_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ADBAR: {mask: 0xffff8000, value: 0x38720000, op: ADBAR, args: instArgs{arg_hint_14_0}},
|
||||
ADBCL: {mask: 0xffff8000, value: 0x002a8000, op: ADBCL, args: instArgs{arg_code_14_0}},
|
||||
ADIV_D: {mask: 0xffff8000, value: 0x00220000, op: ADIV_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ADIV_DU: {mask: 0xffff8000, value: 0x00230000, op: ADIV_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ADIV_W: {mask: 0xffff8000, value: 0x00200000, op: ADIV_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ADIV_WU: {mask: 0xffff8000, value: 0x00210000, op: ADIV_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AERTN: {mask: 0xffffffff, value: 0x06483800, op: AERTN, args: instArgs{}},
|
||||
AEXT_W_B: {mask: 0xfffffc00, value: 0x00005c00, op: AEXT_W_B, args: instArgs{arg_rd, arg_rj}},
|
||||
AEXT_W_H: {mask: 0xfffffc00, value: 0x00005800, op: AEXT_W_H, args: instArgs{arg_rd, arg_rj}},
|
||||
AFABS_D: {mask: 0xfffffc00, value: 0x01140800, op: AFABS_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFABS_S: {mask: 0xfffffc00, value: 0x01140400, op: AFABS_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFADD_D: {mask: 0xffff8000, value: 0x01010000, op: AFADD_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFADD_S: {mask: 0xffff8000, value: 0x01008000, op: AFADD_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFCLASS_D: {mask: 0xfffffc00, value: 0x01143800, op: AFCLASS_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFCLASS_S: {mask: 0xfffffc00, value: 0x01143400, op: AFCLASS_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFCMP_CAF_D: {mask: 0xffff8018, value: 0x0c200000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
AFCMP_CAF_S: {mask: 0xffff8018, value: 0x0c100000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
AFCMP_CEQ_D: {mask: 0xffff8018, value: 0x0c220000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
@@ -984,235 +984,235 @@ var _AOpContextTable = [...]_OpContextType{
|
||||
AFCMP_SUNE_S: {mask: 0xffff8018, value: 0x0c1c8000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
AFCMP_SUN_D: {mask: 0xffff8018, value: 0x0c248000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
AFCMP_SUN_S: {mask: 0xffff8018, value: 0x0c148000, args: instArgs{arg_cd, arg_fj, arg_fk}},
|
||||
AFCOPYSIGN_D: {mask: 0xffff8000, value: 0x01130000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFCOPYSIGN_S: {mask: 0xffff8000, value: 0x01128000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFCVT_D_S: {mask: 0xfffffc00, value: 0x01192400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFCVT_S_D: {mask: 0xfffffc00, value: 0x01191800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFDIV_D: {mask: 0xffff8000, value: 0x01070000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFDIV_S: {mask: 0xffff8000, value: 0x01068000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFFINT_D_L: {mask: 0xfffffc00, value: 0x011d2800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_D_W: {mask: 0xfffffc00, value: 0x011d2000, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_S_L: {mask: 0xfffffc00, value: 0x011d1800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_S_W: {mask: 0xfffffc00, value: 0x011d1000, args: instArgs{arg_fd, arg_fj}},
|
||||
AFLDGT_D: {mask: 0xffff8000, value: 0x38748000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDGT_S: {mask: 0xffff8000, value: 0x38740000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDLE_D: {mask: 0xffff8000, value: 0x38758000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDLE_S: {mask: 0xffff8000, value: 0x38750000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDX_D: {mask: 0xffff8000, value: 0x38340000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDX_S: {mask: 0xffff8000, value: 0x38300000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLD_D: {mask: 0xffc00000, value: 0x2b800000, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFLD_S: {mask: 0xffc00000, value: 0x2b000000, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFLOGB_D: {mask: 0xfffffc00, value: 0x01142800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFLOGB_S: {mask: 0xfffffc00, value: 0x01142400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMADD_D: {mask: 0xfff00000, value: 0x08200000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMADD_S: {mask: 0xfff00000, value: 0x08100000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMAXA_D: {mask: 0xffff8000, value: 0x010d0000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAXA_S: {mask: 0xffff8000, value: 0x010c8000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAX_D: {mask: 0xffff8000, value: 0x01090000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAX_S: {mask: 0xffff8000, value: 0x01088000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMINA_D: {mask: 0xffff8000, value: 0x010f0000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMINA_S: {mask: 0xffff8000, value: 0x010e8000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMIN_D: {mask: 0xffff8000, value: 0x010b0000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMIN_S: {mask: 0xffff8000, value: 0x010a8000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMOV_D: {mask: 0xfffffc00, value: 0x01149800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMOV_S: {mask: 0xfffffc00, value: 0x01149400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMSUB_D: {mask: 0xfff00000, value: 0x08600000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMSUB_S: {mask: 0xfff00000, value: 0x08500000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMUL_D: {mask: 0xffff8000, value: 0x01050000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMUL_S: {mask: 0xffff8000, value: 0x01048000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFNEG_D: {mask: 0xfffffc00, value: 0x01141800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFNEG_S: {mask: 0xfffffc00, value: 0x01141400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFNMADD_D: {mask: 0xfff00000, value: 0x08a00000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMADD_S: {mask: 0xfff00000, value: 0x08900000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMSUB_D: {mask: 0xfff00000, value: 0x08e00000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMSUB_S: {mask: 0xfff00000, value: 0x08d00000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFRECIPE_D: {mask: 0xfffffc00, value: 0x01147800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIPE_S: {mask: 0xfffffc00, value: 0x01147400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIP_D: {mask: 0xfffffc00, value: 0x01145800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIP_S: {mask: 0xfffffc00, value: 0x01145400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRINT_D: {mask: 0xfffffc00, value: 0x011e4800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRINT_S: {mask: 0xfffffc00, value: 0x011e4400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRTE_D: {mask: 0xfffffc00, value: 0x01148800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRTE_S: {mask: 0xfffffc00, value: 0x01148400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRT_D: {mask: 0xfffffc00, value: 0x01146800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRT_S: {mask: 0xfffffc00, value: 0x01146400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSCALEB_D: {mask: 0xffff8000, value: 0x01110000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSCALEB_S: {mask: 0xffff8000, value: 0x01108000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSEL: {mask: 0xfffc0000, value: 0x0d000000, args: instArgs{arg_fd, arg_fj, arg_fk, arg_ca}},
|
||||
AFSQRT_D: {mask: 0xfffffc00, value: 0x01144800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSQRT_S: {mask: 0xfffffc00, value: 0x01144400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSTGT_D: {mask: 0xffff8000, value: 0x38768000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTGT_S: {mask: 0xffff8000, value: 0x38760000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTLE_D: {mask: 0xffff8000, value: 0x38778000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTLE_S: {mask: 0xffff8000, value: 0x38770000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTX_D: {mask: 0xffff8000, value: 0x383c0000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTX_S: {mask: 0xffff8000, value: 0x38380000, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFST_D: {mask: 0xffc00000, value: 0x2bc00000, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFST_S: {mask: 0xffc00000, value: 0x2b400000, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFSUB_D: {mask: 0xffff8000, value: 0x01030000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSUB_S: {mask: 0xffff8000, value: 0x01028000, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFTINTRM_L_D: {mask: 0xfffffc00, value: 0x011a2800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_L_S: {mask: 0xfffffc00, value: 0x011a2400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_W_D: {mask: 0xfffffc00, value: 0x011a0800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_W_S: {mask: 0xfffffc00, value: 0x011a0400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_L_D: {mask: 0xfffffc00, value: 0x011ae800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_L_S: {mask: 0xfffffc00, value: 0x011ae400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_W_D: {mask: 0xfffffc00, value: 0x011ac800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_W_S: {mask: 0xfffffc00, value: 0x011ac400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_L_D: {mask: 0xfffffc00, value: 0x011a6800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_L_S: {mask: 0xfffffc00, value: 0x011a6400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_W_D: {mask: 0xfffffc00, value: 0x011a4800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_W_S: {mask: 0xfffffc00, value: 0x011a4400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_L_D: {mask: 0xfffffc00, value: 0x011aa800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_L_S: {mask: 0xfffffc00, value: 0x011aa400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_W_D: {mask: 0xfffffc00, value: 0x011a8800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_W_S: {mask: 0xfffffc00, value: 0x011a8400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_L_D: {mask: 0xfffffc00, value: 0x011b2800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_L_S: {mask: 0xfffffc00, value: 0x011b2400, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_W_D: {mask: 0xfffffc00, value: 0x011b0800, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_W_S: {mask: 0xfffffc00, value: 0x011b0400, args: instArgs{arg_fd, arg_fj}},
|
||||
AIBAR: {mask: 0xffff8000, value: 0x38728000, args: instArgs{arg_hint_14_0}},
|
||||
AIDLE: {mask: 0xffff8000, value: 0x06488000, args: instArgs{arg_level_14_0}},
|
||||
AINVTLB: {mask: 0xffff8000, value: 0x06498000, args: instArgs{arg_op_4_0, arg_rj, arg_rk}},
|
||||
AIOCSRRD_B: {mask: 0xfffffc00, value: 0x06480000, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_D: {mask: 0xfffffc00, value: 0x06480c00, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_H: {mask: 0xfffffc00, value: 0x06480400, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_W: {mask: 0xfffffc00, value: 0x06480800, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_B: {mask: 0xfffffc00, value: 0x06481000, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_D: {mask: 0xfffffc00, value: 0x06481c00, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_H: {mask: 0xfffffc00, value: 0x06481400, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_W: {mask: 0xfffffc00, value: 0x06481800, args: instArgs{arg_rd, arg_rj}},
|
||||
AJIRL: {mask: 0xfc000000, value: 0x4c000000, args: instArgs{arg_rd, arg_rj, arg_offset_15_0}},
|
||||
ALDDIR: {mask: 0xfffc0000, value: 0x06400000, args: instArgs{arg_rd, arg_rj, arg_level_17_10}},
|
||||
ALDGT_B: {mask: 0xffff8000, value: 0x38780000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_D: {mask: 0xffff8000, value: 0x38798000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_H: {mask: 0xffff8000, value: 0x38788000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_W: {mask: 0xffff8000, value: 0x38790000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_B: {mask: 0xffff8000, value: 0x387a0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_D: {mask: 0xffff8000, value: 0x387b8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_H: {mask: 0xffff8000, value: 0x387a8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_W: {mask: 0xffff8000, value: 0x387b0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDPTE: {mask: 0xfffc001f, value: 0x06440000, args: instArgs{arg_rj, arg_seq_17_10}},
|
||||
ALDPTR_D: {mask: 0xff000000, value: 0x26000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALDPTR_W: {mask: 0xff000000, value: 0x24000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALDX_B: {mask: 0xffff8000, value: 0x38000000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_BU: {mask: 0xffff8000, value: 0x38200000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_D: {mask: 0xffff8000, value: 0x380c0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_H: {mask: 0xffff8000, value: 0x38040000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_HU: {mask: 0xffff8000, value: 0x38240000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_W: {mask: 0xffff8000, value: 0x38080000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_WU: {mask: 0xffff8000, value: 0x38280000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALD_B: {mask: 0xffc00000, value: 0x28000000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_BU: {mask: 0xffc00000, value: 0x2a000000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_D: {mask: 0xffc00000, value: 0x28c00000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_H: {mask: 0xffc00000, value: 0x28400000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_HU: {mask: 0xffc00000, value: 0x2a400000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_W: {mask: 0xffc00000, value: 0x28800000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_WU: {mask: 0xffc00000, value: 0x2a800000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALLACQ_D: {mask: 0xfffffc00, value: 0x38578800, args: instArgs{arg_rd, arg_rj}},
|
||||
ALLACQ_W: {mask: 0xfffffc00, value: 0x38578000, args: instArgs{arg_rd, arg_rj}},
|
||||
ALL_D: {mask: 0xff000000, value: 0x22000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALL_W: {mask: 0xff000000, value: 0x20000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALU12I_W: {mask: 0xfe000000, value: 0x14000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
ALU32I_D: {mask: 0xfe000000, value: 0x16000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
ALU52I_D: {mask: 0xffc00000, value: 0x03000000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AMASKEQZ: {mask: 0xffff8000, value: 0x00130000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMASKNEZ: {mask: 0xffff8000, value: 0x00138000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_D: {mask: 0xffff8000, value: 0x00228000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_DU: {mask: 0xffff8000, value: 0x00238000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_W: {mask: 0xffff8000, value: 0x00208000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_WU: {mask: 0xffff8000, value: 0x00218000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOVCF2FR: {mask: 0xffffff00, value: 0x0114d400, args: instArgs{arg_fd, arg_cj}},
|
||||
AMOVCF2GR: {mask: 0xffffff00, value: 0x0114dc00, args: instArgs{arg_rd, arg_cj}},
|
||||
AMOVFCSR2GR: {mask: 0xfffffc00, value: 0x0114c800, args: instArgs{arg_rd, arg_fcsr_9_5}},
|
||||
AMOVFR2CF: {mask: 0xfffffc18, value: 0x0114d000, args: instArgs{arg_cd, arg_fj}},
|
||||
AMOVFR2GR_D: {mask: 0xfffffc00, value: 0x0114b800, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVFR2GR_S: {mask: 0xfffffc00, value: 0x0114b400, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVFRH2GR_S: {mask: 0xfffffc00, value: 0x0114bc00, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVGR2CF: {mask: 0xfffffc18, value: 0x0114d800, args: instArgs{arg_cd, arg_rj}},
|
||||
AMOVGR2FCSR: {mask: 0xfffffc00, value: 0x0114c000, args: instArgs{arg_fcsr_4_0, arg_rj}},
|
||||
AMOVGR2FRH_W: {mask: 0xfffffc00, value: 0x0114ac00, args: instArgs{arg_fd, arg_rj}},
|
||||
AMOVGR2FR_D: {mask: 0xfffffc00, value: 0x0114a800, args: instArgs{arg_fd, arg_rj}},
|
||||
AMOVGR2FR_W: {mask: 0xfffffc00, value: 0x0114a400, args: instArgs{arg_fd, arg_rj}},
|
||||
AMULH_D: {mask: 0xffff8000, value: 0x001e0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_DU: {mask: 0xffff8000, value: 0x001e8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_W: {mask: 0xffff8000, value: 0x001c8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_WU: {mask: 0xffff8000, value: 0x001d0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULW_D_W: {mask: 0xffff8000, value: 0x001f0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULW_D_WU: {mask: 0xffff8000, value: 0x001f8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMUL_D: {mask: 0xffff8000, value: 0x001d8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMUL_W: {mask: 0xffff8000, value: 0x001c0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ANOR: {mask: 0xffff8000, value: 0x00140000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AOR: {mask: 0xffff8000, value: 0x00150000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AORI: {mask: 0xffc00000, value: 0x03800000, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
|
||||
AORN: {mask: 0xffff8000, value: 0x00160000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
APCADDI: {mask: 0xfe000000, value: 0x18000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCADDU12I: {mask: 0xfe000000, value: 0x1c000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCADDU18I: {mask: 0xfe000000, value: 0x1e000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCALAU12I: {mask: 0xfe000000, value: 0x1a000000, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APRELD: {mask: 0xffc00000, value: 0x2ac00000, args: instArgs{arg_hint_4_0, arg_rj, arg_si12_21_10}},
|
||||
APRELDX: {mask: 0xffff8000, value: 0x382c0000, args: instArgs{arg_hint_4_0, arg_rj, arg_rk}},
|
||||
ARDTIMEH_W: {mask: 0xfffffc00, value: 0x00006400, args: instArgs{arg_rd, arg_rj}},
|
||||
ARDTIMEL_W: {mask: 0xfffffc00, value: 0x00006000, args: instArgs{arg_rd, arg_rj}},
|
||||
ARDTIME_D: {mask: 0xfffffc00, value: 0x00006800, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_2H: {mask: 0xfffffc00, value: 0x00003000, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_2W: {mask: 0xfffffc00, value: 0x00003800, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_4H: {mask: 0xfffffc00, value: 0x00003400, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_D: {mask: 0xfffffc00, value: 0x00003c00, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVH_2W: {mask: 0xfffffc00, value: 0x00004000, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVH_D: {mask: 0xfffffc00, value: 0x00004400, args: instArgs{arg_rd, arg_rj}},
|
||||
AROTRI_D: {mask: 0xffff0000, value: 0x004d0000, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
AROTRI_W: {mask: 0xffff8000, value: 0x004c8000, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
AROTR_D: {mask: 0xffff8000, value: 0x001b8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AROTR_W: {mask: 0xffff8000, value: 0x001b0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASCREL_D: {mask: 0xfffffc00, value: 0x38578c00, args: instArgs{arg_rd, arg_rj}},
|
||||
ASCREL_W: {mask: 0xfffffc00, value: 0x38578400, args: instArgs{arg_rd, arg_rj}},
|
||||
ASC_D: {mask: 0xff000000, value: 0x23000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASC_Q: {mask: 0xffff8000, value: 0x38570000, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
ASC_W: {mask: 0xff000000, value: 0x21000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASLLI_D: {mask: 0xffff0000, value: 0x00410000, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASLLI_W: {mask: 0xffff8000, value: 0x00408000, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASLL_D: {mask: 0xffff8000, value: 0x00188000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLL_W: {mask: 0xffff8000, value: 0x00170000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLT: {mask: 0xffff8000, value: 0x00120000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLTI: {mask: 0xffc00000, value: 0x02000000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASLTU: {mask: 0xffff8000, value: 0x00128000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLTUI: {mask: 0xffc00000, value: 0x02400000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASRAI_D: {mask: 0xffff0000, value: 0x00490000, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASRAI_W: {mask: 0xffff8000, value: 0x00488000, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASRA_D: {mask: 0xffff8000, value: 0x00198000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRA_W: {mask: 0xffff8000, value: 0x00180000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRLI_D: {mask: 0xffff0000, value: 0x00450000, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASRLI_W: {mask: 0xffff8000, value: 0x00448000, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASRL_D: {mask: 0xffff8000, value: 0x00190000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRL_W: {mask: 0xffff8000, value: 0x00178000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_B: {mask: 0xffff8000, value: 0x387c0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_D: {mask: 0xffff8000, value: 0x387d8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_H: {mask: 0xffff8000, value: 0x387c8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_W: {mask: 0xffff8000, value: 0x387d0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_B: {mask: 0xffff8000, value: 0x387e0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_D: {mask: 0xffff8000, value: 0x387f8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_H: {mask: 0xffff8000, value: 0x387e8000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_W: {mask: 0xffff8000, value: 0x387f0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTPTR_D: {mask: 0xff000000, value: 0x27000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASTPTR_W: {mask: 0xff000000, value: 0x25000000, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASTX_B: {mask: 0xffff8000, value: 0x38100000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_D: {mask: 0xffff8000, value: 0x381c0000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_H: {mask: 0xffff8000, value: 0x38140000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_W: {mask: 0xffff8000, value: 0x38180000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AST_B: {mask: 0xffc00000, value: 0x29000000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_D: {mask: 0xffc00000, value: 0x29c00000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_H: {mask: 0xffc00000, value: 0x29400000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_W: {mask: 0xffc00000, value: 0x29800000, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASUB_D: {mask: 0xffff8000, value: 0x00118000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASUB_W: {mask: 0xffff8000, value: 0x00110000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASYSCALL: {mask: 0xffff8000, value: 0x002b0000, args: instArgs{arg_code_14_0}},
|
||||
ATLBCLR: {mask: 0xffffffff, value: 0x06482000, args: instArgs{}},
|
||||
ATLBFILL: {mask: 0xffffffff, value: 0x06483400, args: instArgs{}},
|
||||
ATLBFLUSH: {mask: 0xffffffff, value: 0x06482400, args: instArgs{}},
|
||||
ATLBRD: {mask: 0xffffffff, value: 0x06482c00, args: instArgs{}},
|
||||
ATLBSRCH: {mask: 0xffffffff, value: 0x06482800, args: instArgs{}},
|
||||
ATLBWR: {mask: 0xffffffff, value: 0x06483000, args: instArgs{}},
|
||||
AXOR: {mask: 0xffff8000, value: 0x00158000, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AXORI: {mask: 0xffc00000, value: 0x03c00000, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
|
||||
AFCOPYSIGN_D: {mask: 0xffff8000, value: 0x01130000, op: AFCOPYSIGN_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFCOPYSIGN_S: {mask: 0xffff8000, value: 0x01128000, op: AFCOPYSIGN_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFCVT_D_S: {mask: 0xfffffc00, value: 0x01192400, op: AFCVT_D_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFCVT_S_D: {mask: 0xfffffc00, value: 0x01191800, op: AFCVT_S_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFDIV_D: {mask: 0xffff8000, value: 0x01070000, op: AFDIV_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFDIV_S: {mask: 0xffff8000, value: 0x01068000, op: AFDIV_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFFINT_D_L: {mask: 0xfffffc00, value: 0x011d2800, op: AFFINT_D_L, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_D_W: {mask: 0xfffffc00, value: 0x011d2000, op: AFFINT_D_W, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_S_L: {mask: 0xfffffc00, value: 0x011d1800, op: AFFINT_S_L, args: instArgs{arg_fd, arg_fj}},
|
||||
AFFINT_S_W: {mask: 0xfffffc00, value: 0x011d1000, op: AFFINT_S_W, args: instArgs{arg_fd, arg_fj}},
|
||||
AFLDGT_D: {mask: 0xffff8000, value: 0x38748000, op: AFLDGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDGT_S: {mask: 0xffff8000, value: 0x38740000, op: AFLDGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDLE_D: {mask: 0xffff8000, value: 0x38758000, op: AFLDLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDLE_S: {mask: 0xffff8000, value: 0x38750000, op: AFLDLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDX_D: {mask: 0xffff8000, value: 0x38340000, op: AFLDX_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLDX_S: {mask: 0xffff8000, value: 0x38300000, op: AFLDX_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFLD_D: {mask: 0xffc00000, value: 0x2b800000, op: AFLD_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFLD_S: {mask: 0xffc00000, value: 0x2b000000, op: AFLD_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFLOGB_D: {mask: 0xfffffc00, value: 0x01142800, op: AFLOGB_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFLOGB_S: {mask: 0xfffffc00, value: 0x01142400, op: AFLOGB_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMADD_D: {mask: 0xfff00000, value: 0x08200000, op: AFMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMADD_S: {mask: 0xfff00000, value: 0x08100000, op: AFMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMAXA_D: {mask: 0xffff8000, value: 0x010d0000, op: AFMAXA_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAXA_S: {mask: 0xffff8000, value: 0x010c8000, op: AFMAXA_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAX_D: {mask: 0xffff8000, value: 0x01090000, op: AFMAX_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMAX_S: {mask: 0xffff8000, value: 0x01088000, op: AFMAX_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMINA_D: {mask: 0xffff8000, value: 0x010f0000, op: AFMINA_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMINA_S: {mask: 0xffff8000, value: 0x010e8000, op: AFMINA_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMIN_D: {mask: 0xffff8000, value: 0x010b0000, op: AFMIN_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMIN_S: {mask: 0xffff8000, value: 0x010a8000, op: AFMIN_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMOV_D: {mask: 0xfffffc00, value: 0x01149800, op: AFMOV_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMOV_S: {mask: 0xfffffc00, value: 0x01149400, op: AFMOV_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFMSUB_D: {mask: 0xfff00000, value: 0x08600000, op: AFMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMSUB_S: {mask: 0xfff00000, value: 0x08500000, op: AFMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFMUL_D: {mask: 0xffff8000, value: 0x01050000, op: AFMUL_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFMUL_S: {mask: 0xffff8000, value: 0x01048000, op: AFMUL_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFNEG_D: {mask: 0xfffffc00, value: 0x01141800, op: AFNEG_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFNEG_S: {mask: 0xfffffc00, value: 0x01141400, op: AFNEG_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFNMADD_D: {mask: 0xfff00000, value: 0x08a00000, op: AFNMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMADD_S: {mask: 0xfff00000, value: 0x08900000, op: AFNMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMSUB_D: {mask: 0xfff00000, value: 0x08e00000, op: AFNMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFNMSUB_S: {mask: 0xfff00000, value: 0x08d00000, op: AFNMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
|
||||
AFRECIPE_D: {mask: 0xfffffc00, value: 0x01147800, op: AFRECIPE_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIPE_S: {mask: 0xfffffc00, value: 0x01147400, op: AFRECIPE_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIP_D: {mask: 0xfffffc00, value: 0x01145800, op: AFRECIP_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRECIP_S: {mask: 0xfffffc00, value: 0x01145400, op: AFRECIP_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRINT_D: {mask: 0xfffffc00, value: 0x011e4800, op: AFRINT_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRINT_S: {mask: 0xfffffc00, value: 0x011e4400, op: AFRINT_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRTE_D: {mask: 0xfffffc00, value: 0x01148800, op: AFRSQRTE_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRTE_S: {mask: 0xfffffc00, value: 0x01148400, op: AFRSQRTE_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRT_D: {mask: 0xfffffc00, value: 0x01146800, op: AFRSQRT_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFRSQRT_S: {mask: 0xfffffc00, value: 0x01146400, op: AFRSQRT_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSCALEB_D: {mask: 0xffff8000, value: 0x01110000, op: AFSCALEB_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSCALEB_S: {mask: 0xffff8000, value: 0x01108000, op: AFSCALEB_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSEL: {mask: 0xfffc0000, value: 0x0d000000, op: AFSEL, args: instArgs{arg_fd, arg_fj, arg_fk, arg_ca}},
|
||||
AFSQRT_D: {mask: 0xfffffc00, value: 0x01144800, op: AFSQRT_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSQRT_S: {mask: 0xfffffc00, value: 0x01144400, op: AFSQRT_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFSTGT_D: {mask: 0xffff8000, value: 0x38768000, op: AFSTGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTGT_S: {mask: 0xffff8000, value: 0x38760000, op: AFSTGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTLE_D: {mask: 0xffff8000, value: 0x38778000, op: AFSTLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTLE_S: {mask: 0xffff8000, value: 0x38770000, op: AFSTLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTX_D: {mask: 0xffff8000, value: 0x383c0000, op: AFSTX_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFSTX_S: {mask: 0xffff8000, value: 0x38380000, op: AFSTX_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
|
||||
AFST_D: {mask: 0xffc00000, value: 0x2bc00000, op: AFST_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFST_S: {mask: 0xffc00000, value: 0x2b400000, op: AFST_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
|
||||
AFSUB_D: {mask: 0xffff8000, value: 0x01030000, op: AFSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFSUB_S: {mask: 0xffff8000, value: 0x01028000, op: AFSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
|
||||
AFTINTRM_L_D: {mask: 0xfffffc00, value: 0x011a2800, op: AFTINTRM_L_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_L_S: {mask: 0xfffffc00, value: 0x011a2400, op: AFTINTRM_L_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_W_D: {mask: 0xfffffc00, value: 0x011a0800, op: AFTINTRM_W_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRM_W_S: {mask: 0xfffffc00, value: 0x011a0400, op: AFTINTRM_W_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_L_D: {mask: 0xfffffc00, value: 0x011ae800, op: AFTINTRNE_L_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_L_S: {mask: 0xfffffc00, value: 0x011ae400, op: AFTINTRNE_L_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_W_D: {mask: 0xfffffc00, value: 0x011ac800, op: AFTINTRNE_W_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRNE_W_S: {mask: 0xfffffc00, value: 0x011ac400, op: AFTINTRNE_W_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_L_D: {mask: 0xfffffc00, value: 0x011a6800, op: AFTINTRP_L_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_L_S: {mask: 0xfffffc00, value: 0x011a6400, op: AFTINTRP_L_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_W_D: {mask: 0xfffffc00, value: 0x011a4800, op: AFTINTRP_W_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRP_W_S: {mask: 0xfffffc00, value: 0x011a4400, op: AFTINTRP_W_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_L_D: {mask: 0xfffffc00, value: 0x011aa800, op: AFTINTRZ_L_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_L_S: {mask: 0xfffffc00, value: 0x011aa400, op: AFTINTRZ_L_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_W_D: {mask: 0xfffffc00, value: 0x011a8800, op: AFTINTRZ_W_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINTRZ_W_S: {mask: 0xfffffc00, value: 0x011a8400, op: AFTINTRZ_W_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_L_D: {mask: 0xfffffc00, value: 0x011b2800, op: AFTINT_L_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_L_S: {mask: 0xfffffc00, value: 0x011b2400, op: AFTINT_L_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_W_D: {mask: 0xfffffc00, value: 0x011b0800, op: AFTINT_W_D, args: instArgs{arg_fd, arg_fj}},
|
||||
AFTINT_W_S: {mask: 0xfffffc00, value: 0x011b0400, op: AFTINT_W_S, args: instArgs{arg_fd, arg_fj}},
|
||||
AIBAR: {mask: 0xffff8000, value: 0x38728000, op: AIBAR, args: instArgs{arg_hint_14_0}},
|
||||
AIDLE: {mask: 0xffff8000, value: 0x06488000, op: AIDLE, args: instArgs{arg_level_14_0}},
|
||||
AINVTLB: {mask: 0xffff8000, value: 0x06498000, op: AINVTLB, args: instArgs{arg_op_4_0, arg_rj, arg_rk}},
|
||||
AIOCSRRD_B: {mask: 0xfffffc00, value: 0x06480000, op: AIOCSRRD_B, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_D: {mask: 0xfffffc00, value: 0x06480c00, op: AIOCSRRD_D, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_H: {mask: 0xfffffc00, value: 0x06480400, op: AIOCSRRD_H, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRRD_W: {mask: 0xfffffc00, value: 0x06480800, op: AIOCSRRD_W, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_B: {mask: 0xfffffc00, value: 0x06481000, op: AIOCSRWR_B, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_D: {mask: 0xfffffc00, value: 0x06481c00, op: AIOCSRWR_D, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_H: {mask: 0xfffffc00, value: 0x06481400, op: AIOCSRWR_H, args: instArgs{arg_rd, arg_rj}},
|
||||
AIOCSRWR_W: {mask: 0xfffffc00, value: 0x06481800, op: AIOCSRWR_W, args: instArgs{arg_rd, arg_rj}},
|
||||
AJIRL: {mask: 0xfc000000, value: 0x4c000000, op: AJIRL, args: instArgs{arg_rd, arg_rj, arg_offset_15_0}},
|
||||
ALDDIR: {mask: 0xfffc0000, value: 0x06400000, op: ALDDIR, args: instArgs{arg_rd, arg_rj, arg_level_17_10}},
|
||||
ALDGT_B: {mask: 0xffff8000, value: 0x38780000, op: ALDGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_D: {mask: 0xffff8000, value: 0x38798000, op: ALDGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_H: {mask: 0xffff8000, value: 0x38788000, op: ALDGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDGT_W: {mask: 0xffff8000, value: 0x38790000, op: ALDGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_B: {mask: 0xffff8000, value: 0x387a0000, op: ALDLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_D: {mask: 0xffff8000, value: 0x387b8000, op: ALDLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_H: {mask: 0xffff8000, value: 0x387a8000, op: ALDLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDLE_W: {mask: 0xffff8000, value: 0x387b0000, op: ALDLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDPTE: {mask: 0xfffc001f, value: 0x06440000, op: ALDPTE, args: instArgs{arg_rj, arg_seq_17_10}},
|
||||
ALDPTR_D: {mask: 0xff000000, value: 0x26000000, op: ALDPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALDPTR_W: {mask: 0xff000000, value: 0x24000000, op: ALDPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALDX_B: {mask: 0xffff8000, value: 0x38000000, op: ALDX_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_BU: {mask: 0xffff8000, value: 0x38200000, op: ALDX_BU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_D: {mask: 0xffff8000, value: 0x380c0000, op: ALDX_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_H: {mask: 0xffff8000, value: 0x38040000, op: ALDX_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_HU: {mask: 0xffff8000, value: 0x38240000, op: ALDX_HU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_W: {mask: 0xffff8000, value: 0x38080000, op: ALDX_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALDX_WU: {mask: 0xffff8000, value: 0x38280000, op: ALDX_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ALD_B: {mask: 0xffc00000, value: 0x28000000, op: ALD_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_BU: {mask: 0xffc00000, value: 0x2a000000, op: ALD_BU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_D: {mask: 0xffc00000, value: 0x28c00000, op: ALD_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_H: {mask: 0xffc00000, value: 0x28400000, op: ALD_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_HU: {mask: 0xffc00000, value: 0x2a400000, op: ALD_HU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_W: {mask: 0xffc00000, value: 0x28800000, op: ALD_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALD_WU: {mask: 0xffc00000, value: 0x2a800000, op: ALD_WU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ALLACQ_D: {mask: 0xfffffc00, value: 0x38578800, op: ALLACQ_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ALLACQ_W: {mask: 0xfffffc00, value: 0x38578000, op: ALLACQ_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ALL_D: {mask: 0xff000000, value: 0x22000000, op: ALL_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALL_W: {mask: 0xff000000, value: 0x20000000, op: ALL_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ALU12I_W: {mask: 0xfe000000, value: 0x14000000, op: ALU12I_W, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
ALU32I_D: {mask: 0xfe000000, value: 0x16000000, op: ALU32I_D, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
ALU52I_D: {mask: 0xffc00000, value: 0x03000000, op: ALU52I_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AMASKEQZ: {mask: 0xffff8000, value: 0x00130000, op: AMASKEQZ, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMASKNEZ: {mask: 0xffff8000, value: 0x00138000, op: AMASKNEZ, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_D: {mask: 0xffff8000, value: 0x00228000, op: AMOD_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_DU: {mask: 0xffff8000, value: 0x00238000, op: AMOD_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_W: {mask: 0xffff8000, value: 0x00208000, op: AMOD_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOD_WU: {mask: 0xffff8000, value: 0x00218000, op: AMOD_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMOVCF2FR: {mask: 0xffffff00, value: 0x0114d400, op: AMOVCF2FR, args: instArgs{arg_fd, arg_cj}},
|
||||
AMOVCF2GR: {mask: 0xffffff00, value: 0x0114dc00, op: AMOVCF2GR, args: instArgs{arg_rd, arg_cj}},
|
||||
AMOVFCSR2GR: {mask: 0xfffffc00, value: 0x0114c800, op: AMOVFCSR2GR, args: instArgs{arg_rd, arg_fcsr_9_5}},
|
||||
AMOVFR2CF: {mask: 0xfffffc18, value: 0x0114d000, op: AMOVFR2CF, args: instArgs{arg_cd, arg_fj}},
|
||||
AMOVFR2GR_D: {mask: 0xfffffc00, value: 0x0114b800, op: AMOVFR2GR_D, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVFR2GR_S: {mask: 0xfffffc00, value: 0x0114b400, op: AMOVFR2GR_S, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVFRH2GR_S: {mask: 0xfffffc00, value: 0x0114bc00, op: AMOVFRH2GR_S, args: instArgs{arg_rd, arg_fj}},
|
||||
AMOVGR2CF: {mask: 0xfffffc18, value: 0x0114d800, op: AMOVGR2CF, args: instArgs{arg_cd, arg_rj}},
|
||||
AMOVGR2FCSR: {mask: 0xfffffc00, value: 0x0114c000, op: AMOVGR2FCSR, args: instArgs{arg_fcsr_4_0, arg_rj}},
|
||||
AMOVGR2FRH_W: {mask: 0xfffffc00, value: 0x0114ac00, op: AMOVGR2FRH_W, args: instArgs{arg_fd, arg_rj}},
|
||||
AMOVGR2FR_D: {mask: 0xfffffc00, value: 0x0114a800, op: AMOVGR2FR_D, args: instArgs{arg_fd, arg_rj}},
|
||||
AMOVGR2FR_W: {mask: 0xfffffc00, value: 0x0114a400, op: AMOVGR2FR_W, args: instArgs{arg_fd, arg_rj}},
|
||||
AMULH_D: {mask: 0xffff8000, value: 0x001e0000, op: AMULH_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_DU: {mask: 0xffff8000, value: 0x001e8000, op: AMULH_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_W: {mask: 0xffff8000, value: 0x001c8000, op: AMULH_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULH_WU: {mask: 0xffff8000, value: 0x001d0000, op: AMULH_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULW_D_W: {mask: 0xffff8000, value: 0x001f0000, op: AMULW_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMULW_D_WU: {mask: 0xffff8000, value: 0x001f8000, op: AMULW_D_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMUL_D: {mask: 0xffff8000, value: 0x001d8000, op: AMUL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AMUL_W: {mask: 0xffff8000, value: 0x001c0000, op: AMUL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ANOR: {mask: 0xffff8000, value: 0x00140000, op: ANOR, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AOR: {mask: 0xffff8000, value: 0x00150000, op: AOR, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AORI: {mask: 0xffc00000, value: 0x03800000, op: AORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
|
||||
AORN: {mask: 0xffff8000, value: 0x00160000, op: AORN, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
APCADDI: {mask: 0xfe000000, value: 0x18000000, op: APCADDI, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCADDU12I: {mask: 0xfe000000, value: 0x1c000000, op: APCADDU12I, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCADDU18I: {mask: 0xfe000000, value: 0x1e000000, op: APCADDU18I, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APCALAU12I: {mask: 0xfe000000, value: 0x1a000000, op: APCALAU12I, args: instArgs{arg_rd, arg_si20_24_5}},
|
||||
APRELD: {mask: 0xffc00000, value: 0x2ac00000, op: APRELD, args: instArgs{arg_hint_4_0, arg_rj, arg_si12_21_10}},
|
||||
APRELDX: {mask: 0xffff8000, value: 0x382c0000, op: APRELDX, args: instArgs{arg_hint_4_0, arg_rj, arg_rk}},
|
||||
ARDTIMEH_W: {mask: 0xfffffc00, value: 0x00006400, op: ARDTIMEH_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ARDTIMEL_W: {mask: 0xfffffc00, value: 0x00006000, op: ARDTIMEL_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ARDTIME_D: {mask: 0xfffffc00, value: 0x00006800, op: ARDTIME_D, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_2H: {mask: 0xfffffc00, value: 0x00003000, op: AREVB_2H, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_2W: {mask: 0xfffffc00, value: 0x00003800, op: AREVB_2W, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_4H: {mask: 0xfffffc00, value: 0x00003400, op: AREVB_4H, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVB_D: {mask: 0xfffffc00, value: 0x00003c00, op: AREVB_D, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVH_2W: {mask: 0xfffffc00, value: 0x00004000, op: AREVH_2W, args: instArgs{arg_rd, arg_rj}},
|
||||
AREVH_D: {mask: 0xfffffc00, value: 0x00004400, op: AREVH_D, args: instArgs{arg_rd, arg_rj}},
|
||||
AROTRI_D: {mask: 0xffff0000, value: 0x004d0000, op: AROTRI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
AROTRI_W: {mask: 0xffff8000, value: 0x004c8000, op: AROTRI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
AROTR_D: {mask: 0xffff8000, value: 0x001b8000, op: AROTR_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AROTR_W: {mask: 0xffff8000, value: 0x001b0000, op: AROTR_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASCREL_D: {mask: 0xfffffc00, value: 0x38578c00, op: ASCREL_D, args: instArgs{arg_rd, arg_rj}},
|
||||
ASCREL_W: {mask: 0xfffffc00, value: 0x38578400, op: ASCREL_W, args: instArgs{arg_rd, arg_rj}},
|
||||
ASC_D: {mask: 0xff000000, value: 0x23000000, op: ASC_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASC_Q: {mask: 0xffff8000, value: 0x38570000, op: ASC_Q, args: instArgs{arg_rd, arg_rk, arg_rj}},
|
||||
ASC_W: {mask: 0xff000000, value: 0x21000000, op: ASC_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASLLI_D: {mask: 0xffff0000, value: 0x00410000, op: ASLLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASLLI_W: {mask: 0xffff8000, value: 0x00408000, op: ASLLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASLL_D: {mask: 0xffff8000, value: 0x00188000, op: ASLL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLL_W: {mask: 0xffff8000, value: 0x00170000, op: ASLL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLT: {mask: 0xffff8000, value: 0x00120000, op: ASLT, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLTI: {mask: 0xffc00000, value: 0x02000000, op: ASLTI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASLTU: {mask: 0xffff8000, value: 0x00128000, op: ASLTU, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASLTUI: {mask: 0xffc00000, value: 0x02400000, op: ASLTUI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASRAI_D: {mask: 0xffff0000, value: 0x00490000, op: ASRAI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASRAI_W: {mask: 0xffff8000, value: 0x00488000, op: ASRAI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASRA_D: {mask: 0xffff8000, value: 0x00198000, op: ASRA_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRA_W: {mask: 0xffff8000, value: 0x00180000, op: ASRA_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRLI_D: {mask: 0xffff0000, value: 0x00450000, op: ASRLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
|
||||
ASRLI_W: {mask: 0xffff8000, value: 0x00448000, op: ASRLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
|
||||
ASRL_D: {mask: 0xffff8000, value: 0x00190000, op: ASRL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASRL_W: {mask: 0xffff8000, value: 0x00178000, op: ASRL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_B: {mask: 0xffff8000, value: 0x387c0000, op: ASTGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_D: {mask: 0xffff8000, value: 0x387d8000, op: ASTGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_H: {mask: 0xffff8000, value: 0x387c8000, op: ASTGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTGT_W: {mask: 0xffff8000, value: 0x387d0000, op: ASTGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_B: {mask: 0xffff8000, value: 0x387e0000, op: ASTLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_D: {mask: 0xffff8000, value: 0x387f8000, op: ASTLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_H: {mask: 0xffff8000, value: 0x387e8000, op: ASTLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTLE_W: {mask: 0xffff8000, value: 0x387f0000, op: ASTLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTPTR_D: {mask: 0xff000000, value: 0x27000000, op: ASTPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASTPTR_W: {mask: 0xff000000, value: 0x25000000, op: ASTPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
|
||||
ASTX_B: {mask: 0xffff8000, value: 0x38100000, op: ASTX_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_D: {mask: 0xffff8000, value: 0x381c0000, op: ASTX_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_H: {mask: 0xffff8000, value: 0x38140000, op: ASTX_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASTX_W: {mask: 0xffff8000, value: 0x38180000, op: ASTX_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AST_B: {mask: 0xffc00000, value: 0x29000000, op: AST_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_D: {mask: 0xffc00000, value: 0x29c00000, op: AST_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_H: {mask: 0xffc00000, value: 0x29400000, op: AST_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
AST_W: {mask: 0xffc00000, value: 0x29800000, op: AST_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
|
||||
ASUB_D: {mask: 0xffff8000, value: 0x00118000, op: ASUB_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASUB_W: {mask: 0xffff8000, value: 0x00110000, op: ASUB_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
ASYSCALL: {mask: 0xffff8000, value: 0x002b0000, op: ASYSCALL, args: instArgs{arg_code_14_0}},
|
||||
ATLBCLR: {mask: 0xffffffff, value: 0x06482000, op: ATLBCLR, args: instArgs{}},
|
||||
ATLBFILL: {mask: 0xffffffff, value: 0x06483400, op: ATLBFILL, args: instArgs{}},
|
||||
ATLBFLUSH: {mask: 0xffffffff, value: 0x06482400, op: ATLBFLUSH, args: instArgs{}},
|
||||
ATLBRD: {mask: 0xffffffff, value: 0x06482c00, op: ATLBRD, args: instArgs{}},
|
||||
ATLBSRCH: {mask: 0xffffffff, value: 0x06482800, op: ATLBSRCH, args: instArgs{}},
|
||||
ATLBWR: {mask: 0xffffffff, value: 0x06483000, op: ATLBWR, args: instArgs{}},
|
||||
AXOR: {mask: 0xffff8000, value: 0x00158000, op: AXOR, args: instArgs{arg_rd, arg_rj, arg_rk}},
|
||||
AXORI: {mask: 0xffc00000, value: 0x03c00000, op: AXORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user